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march 2010 doc id 15599 rev 1 1/31 AN2982 application note 1 x 54 w t5 fluorescent lamp ball ast in wide input voltage range using the l6585de - steval-ilb005v2 introduction this application note describes the steval-ilb005v2 demonstration board equipped with the l6585de lighting controller, std7nm50n mosfets and an stth1l06 shottky diode able to drive a 54 w linear t5 fluorescent lamp in a wide input voltage range (88 - 277 vac). the design steps, schematic and board performance are also given. the l6585de lighting controller embeds both the pfc stage and ballast stage suitable for driving all kinds of lamps (t8, t5, t4, cfln,...) and all kinds of topologies having an input power greater than 25 w. new t5 lamps are characterized by very high luminous efficiency and compactness. to optimize their performance, high accuracy in both preheating of the cathodes and steady- state parameters is required. the minimum performance of t5 ballasts together with their minimum safety requirements are summarized in international norms, especially iec61347- 2-3, iec60929, and iec60081. the demand for these lamps is rapidly growing and the l6585de is able to control electronic ballasts meeting all performance specifications and reliability with lo w component count and a small pcb. the steval-ilb005v2 has been developed to drive a 54 w t5-ho lamp. figure 1. steval-ilb005v2 demonstration board !-v www.st.com
contents AN2982 2/31 doc id 15599 rev 1 contents 1 designing the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 design requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 pfc design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.1 output voltage and dynamic ovp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.2 boost choke design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.3 mosfet selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.4 boost diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.5 bulk capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.6 multiplier biasing and selection of pfc current sense resistor . . . . . . . 10 1.2.7 error amplifier compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2.8 input rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.9 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.10 input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 ballast stage design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 resonant network and operating point design . . . . . . . . . . . . . . . . . . . . . 15 2.2 selection of parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 half-bridge design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 end of life detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5 ic power supply design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 demonstration board schematic and bill of material . . . . . . . . . . . . . . 23 3.1 demonstration board performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 ballast stage performance and reliability . . . . . . . . . . . . . . . . . . . . . . . . . 27 4 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AN2982 list of figures doc id 15599 rev 1 3/31 list of figures figure 1. steval-ilb005v2 demonstr ation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. pfc mosfet frequencies along mains half period (fmains = 50 hz) for various input voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. summary of pfc mosfet power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. multiplier bias points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. bode plot with simple compensation network: |gloop|max < 35db . . . . . . . . . . . . . . . . . . 12 figure 8. bode plot with enhanced compensation network: |g loop |max < 35 db and f margin > 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. complete emi filter (differential mode inductors are not present in this design). . . . . . . . . 14 figure 10. resonant inverter simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. resonance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. parameters setting block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. blocking capacitor to ground topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. charge pump network and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15. steval-ilb005v2 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 16. input performance - power factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 17. input performance - total harmonic distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 18. emi spectrum at 277 vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 19. emi spectrum at 88 vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 20. steady-state lamp parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 21. startup sequence with open lamp protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 22. ballast anti-choke saturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 23. eol protection (positive deviation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 24. eol protection (negative deviation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
designing the application AN2982 4/31 doc id 15599 rev 1 1 designing the application the steval-ilb005v2 design follows the an2870 design guidelines. in this section the design specifications and the equations used are given. 1.1 design requirements figure 2. typical application schematic table 1. summary of design requirements description values input voltage 88 to 277 vac (110 to 230 vac 20%) mains frequency 50 hz ? 60 hz pf > 0.975 current thd < 10% lamp type t5 -54 w ho (i lamp = 460 marms; v lamp = 117 vrms) max output voltage 900 vrms lamp connection current preheated, c block to ground topology efficiency 90% !-v #boot "//4 (3$ ,3$ /54 6cc 2su # 6 2cp #cp 6out 2hbcs ("#3 ,ballast ,amp #block #res 2eol 2eol #eol %/, %/,0 4#( %/) 2& /3# '.$ 2p 2d #d #ign 2run 2pre #osc #42 #/-0 ).6 :#$ 2ctrh 2ctrl #ctr 2invh 2invl #comp 2zcd 4pfc $boost 0&' 2pfcs 0&##3 2multh 2mult #mult -5,4 ,$% #in #out 6in -pfc -hs -ls 2ectifier "ridge
AN2982 designing the application doc id 15599 rev 1 5/31 1.2 pfc design 1.2.1 output voltage and dynamic ovp the maximum input voltage is equal to: equation 1 an output voltage equal to v out = 420 v is chosen for better pfc performance. choosing r invh = 3 x 2.2 m , the output voltage is equal to: equation 2 the ripple superimposed on v out is chosen equal to 5%. then, the maximum instantaneous output voltage is equal to 441 v and, therefore, the ovp level must be comprised between 450 v and 500 v. ?v ovp = 480 v is chosen and the ctr pi n voltage divider is dimensioned accordingly ?r ctrh = 3 x 825 k equation 3 1.2.2 boost choke design the minimum pfc frequency is chosen equal to f pfc,min > 15 khz. the maximum inductance value is equal to: equation 4 l pfc = 1.5 mh is selected. the following graph depicts the frequencies that are obtained along the mains period for various input voltages. v 7 . 391 2 v 277 v max , in = ? = = ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? + ? = 39839 1 v 52 . 2 v r r r r 1 v 52 . 2 v out invh invl invl invh out r invi 39.7 k = = ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? + ? = 17656 1 v 4 . 3 v r r r r 1 v 4 . 3 v max , out ctrh ctrl ctrl ctrh ovp r invi 18 k = mh 6 . 2 v v 2 1 f p 2 v l v v 2 1 l p 2 v f out in min , pfc in 2 in out in in 2 in min , pfc = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? =
designing the application AN2982 6/31 doc id 15599 rev 1 figure 3. pfc mosfet frequencies along mains half period (f mains = 50 hz) for various input voltages the maximum choke current is equal to: equation 5 a saturation current higher than i l,sat = 2.2 a is used in order to take into account the tolerance of this parameter. the rms current flowing into the choke is equal to: equation 6 the choke form factor is an ef25 core (a e = 52 mm 2 , l e = 58 mm, material n87 or equivalent having b max <320 mt). its design parameters are as follows: equation 7 the maximum power dissipation of the core should be less than 2.5 w in the worst condition. a multi-conductor wire is used in order to reduce the equivalent resistance at high frequency. !-v a 93 . 1 v p 2 2 i min , in in max , l = ? ? = ma 787 v p 3 2 i min , in in rms , l = = mm 63 . 2 l a n 2 l turns / nh 5 . 49 n l a turns 174 a b l i n e 2 0 gap 2 2 l e max max = = ? ? ? ? ? ? ? = = = =
AN2982 designing the application doc id 15599 rev 1 7/31 when the maximum rms current is obtained, the minimum frequency is detected and the rhf of the choke must be less than: equation 8 using a 13 x 0.1 mm 2 wire, 3.5 is obtained. the core losses, at minimum input voltage, are estimated below 0.35 w, therefore the total losses are lower than 2.5 w as expected. the higher the input voltage is, the lower the power dissipation (e.g. at 220 vac the estimate d total power losses are lower than 1.8 w). the transformer ratio can be calculated as: equation 9 considering a maximum zcd current equal to 1 ma, the limiting resistor is: equation 10 1.2.3 mosfet selection the pfc mosfet must have a v bdss = 500 v and a peak drain current greater than i d,max = 2.2 a. the maximum allowed mosfet dissipation is equal to p mos,max = 1 w in all conditions. the total power dissipation is composed of: conduction losses, dominant at low input voltage: equation 11 equation 12 switching losses, directly proportional to the average switching frequency: equation 13 = = 4 i p r 2 rms , l , l max , hf ( ) = < ? > ? ? = 6 m 18 . 14 m v 4 . 1 m v 2 v v in out zcd , aux n sec 29turns = ? ? = zcd max , in zcd i m v 2 r r zcd 65.3 k r zcd 75 k = > 2 on , ds out rms , in 2 rms , in in on , ds 2 rms , mos on , ds cond a 5278 . 0 r v v 9 2 4 6 1 v p 8 r i r p ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? = 2 max , cond ) on ( ds a 5278 . 0 p (max) r < ? ? ? ? ? ? ? ? ? ? ? ? = out rms , in in 2 rms , in sw v v 2 2 1 l p 2 v f
designing the application AN2982 8/31 doc id 15599 rev 1 equation 14 capacitive losses, present only when v in > v out /2 and have their maximum at v in,max the maximum time when the input voltage is greater than v out /2 can be calculated as follows: equation 15 within this interval th e capacitive losses are: equation 16 where = 173 khz and: equation 17 using equation 11 to 17 with the constraint p tot < 1 w, the following parameters are found: ?r ds(on) < 1.4 (p cond at 88 v < 0.75 w) ?t f < 10 ns (p cross at 88 v < 0.10 w) ?c oss < 110 pf (considering c ext and c rss equal respectively 68 pf and 4 pf) the following st mosfets meet these constraints: ?std5nk50z ?std6nk50z ? std7nm50n the std7nm50n has r ds(on) = 1.12 (at 100 c), t f = 9 ns and c oss = 67 pf and therefore is considered suitable for this design . the total power dissipation is shown in figure 4 . 25200 v f t v p v f t p rms , in sw f rms , in in out sw f cross ? = = ms 2 . 8 t f 2 1 t ms 8 . 1 f 2 v 2 2 v arcsin t 1 mains 2 mains rms , in out 1 ? = ? ? ? ? ? ? ? ? ? ? = () ? ? ? ? ? ? ? ? + + + = 2 drain ext oss rss 2 3 drain oss sw cap v c c c 2 1 v c 3 . 3 f p () [ ] v 7 . 209 dt v t sin v 2 2 f 2 v 2 1 t t 2 out rms , in mains drain = ? ? =
AN2982 designing the application doc id 15599 rev 1 9/31 figure 4. summary of pf c mosfet power losses 1.2.4 boost diode selection both the boost diode maximum rms current and the rms current are equal to: equation 18 their average current is equal to: equation 19 the stth1l06 shottky diode is selected, having v rrm = 600 v and an average forward current i f(av) = 1 a. total power dissipation is equal to: equation 20 1.2.5 bulk capacitor selection the ripple superimposed on the output voltage is equal to 20 v: equation 21 !-v ma 222 v v p 2 2 3 4 i rms , in out in rms , d = = p out v out ---------- - 142ma = mw 5 . 134 222 . 0 165 . 0 142 . 0 89 . 0 p 2 d = ? + ? = ma 373 esr c 10 0463 . 2 i esr c v f 4 p v 20 v out 4 rms , c f @ out out mains out out out min , pfc ? + = = ? + ? ? ? = = ?
designing the application AN2982 10/31 doc id 15599 rev 1 the rms value of the bulk capacitor current is: equation 22 considering the first term of equation 21 as dominant, c out > 10.2 f, and then c out = 22 f is selected. the voltage rating of the capacitor is equal to v cout = 450 v and the temperature class is t cout = 105 c. with this value the typical esr is around 2 , adding only 740 mv to the total ripple. 1.2.6 multiplier biasing and selection of pfc current sense resistor the peak values of the input voltage are between 124.4 v and 391.7 v. the ratio between these two values is equal to 3.15. the mult pin is biased to 1 v when input voltage is equal to 124.4 v. if r multh = 3x680 k : equation 23 figure 5. multiplier bias points with v cs,1 = 0.75 v: equation 24 a c mult =1 nf capacitor is used in parallel with r multl for hf noise filtering. ma 373 v p v v p 9 2 32 i 2 out out out rms , in 2 in rms , c out = ? ? ? ? ? ? ? ? ? ? ? ? = = ? = = = k 53 . 16 r kp 1 kp r 00804 . 0 v v kp multh multl pk min , in 1 , mult r multh 16.2 k = !-v = ? ? ? = = 364 . 0 p 2 2 v v i v r in min , in 1 , cs max , l 1 , cs pfccs r pfccs 0.33 =
AN2982 designing the application doc id 15599 rev 1 11/31 1.2.7 error ampl ifier compensation figure 6. control loop block diagram equation 25 where: ?k m = multiplier factor = 0.52 ?k p = mult pin divider = 0.007879 ?r out = equivalent output resistor = 2.693 k ?c out = 22 f using the simplest compensation network (a capacitor placed between the inv and comp pin) whose transfer function is equal to: equation 26 and setting an open loop gain less than 0.001 when frequency is equal to twice the mains frequency , it is possible to calculate the minimum capacitance needed. equation 27 a c comp = 1 f ceramic capacitor could be a good trade-off between performance and cost, but better performance can be obtained using a more complicated structure in order to obtain a phase margin equal to 45. !-v s 029623 . 0 1 1 v 020308 . 0 2 c r s 1 1 r r v v k k 4 1 ) s ( g 2 rms , in out out pfcs out out 2 rms , in p m + ? ? = + = () ? = = m 6 . 6 sc 1 r sc 1 s g comp invh comp comp () () () 001 . 0 s 029623 . 0 1 1 v 020308 . 0 m 6 . 6 sc 1 s g s g s g hz 100 2 s 2 rms , in comp comp loop = + ? ? ? ? ? ? ? ? ? ? ? = ? = =
designing the application AN2982 12/31 doc id 15599 rev 1 figure 7. bode plot with simple compensation network: |gloop| max < 35db for example, an rc-series network is conn ected between the inv and comp pin. the obtained g loop (s) can be written as: equation 28 a phase margin equal to 45 is obtained at vin = 277 vac using c comp =1.5 f and r comp =39 k . at minimum input voltage the phase margin is equal to 85. higher values of c comp or a lower value of c out can also improve the pfc performance. figure 8. bode plot with enhanced compensation network: |g loop | max < 35 db and margin > 45 !-v () () () s 029623 . 0 1 1 v 020308 . 0 m 6 . 6 sc r sc 1 s g s g s g 2 rms , in comp comp comp comp loop + ? ? ? ? ? ? ? ? ? ? ? + = ? = !-v
AN2982 designing the application doc id 15599 rev 1 13/31 1.2.8 input rectifier a 2kbp06m bridge rectifier is ab le to sustain 600 v in revers e condition and 2 a of forward current. its maximum power dissipation is equal to: equation 29 1.2.9 input capacitor let r = 10% be the maximum allowed ratio between the high-frequency ripple amplitude seen at the input of the pfc stage and the mean value of the input current: equation 30 1.2.10 input circuitry the input circuitry is composed of: ? a fuse: avoids damage due to ballast breaking or excessive current from the mains ? an ntc: limits the inrush current which avoids blowing the fuse and reduces the effects of a burst from the mains. this component reduces its resistance at a higher temperature. a 5 ntc (at 25 c) is used ? a varistor (not present): absorbs the energy associated with a mains surge avoiding that v out increases over the rated voltage of the components (c out , mosfets, ic,?) ? an emi filter: an lc network able to reduce the hf noise coming from the application and traveling through the mains. this filter has to filter both the common mode component of the noise (which can be measured between the ac input and the earth) and the differential mode component of the noise (which can be measured between the two ac inputs) the first component (the fuse) is filtered by a cm filter (a current transformer that forces the ac input currents to travel in the opposite way) and two 1 nf capacitor placed between each ac input and earth. the second component (the ntc) is filtered by two capacitors placed across the ac inputs and by the leakage inductance of the cm filter. in fact by using a cm transformer having a high leakage inductance, a differential filtering can be obtained. the differential capacitors are equal to c x = 100 nf, while the cm capacitors are equal to c y = 1 nf. the cm transformer, t cm , is a b82733f series transformer from epcos. w 73 . 1 v v p 2 2 p f (min) rms , in in b = = nf 470 c nf 87 . 401 v f r 2 p c in 2 (min) rms , in sw in min , in min = = ? ? ? =
designing the application AN2982 14/31 doc id 15599 rev 1 figure 9. complete emi filter (differential mode inductors are not present in this design) !-v
AN2982 ballast stage design doc id 15599 rev 1 15/31 2 ballast stage design figure 10. resonant inverter simplified schematic 2.1 resonant network and operating point design equivalent voltage applied to the resonant network: equation 31 l and c are chosen in order to fit the following constraints: preheating voltage has to be less than 240 vac = 339.4 vpk maximum striking voltage is equal to 700 vac nominal lamp voltage = 117 vac nominal lamp current = 0.46 a selecting a common value equal to l res =1.35 mh and c res =4.7 nf, the following parameters are obtained: equation 32 !-v vpk 38 . 267 v 2 v out pk , bal = = ? ? ? ? ? ? ? ? ? ? ? = = = = = = = 4836 . 0 z i v z r q 526 c l z hz 64387 c l 2 1 f 0 run run 0 lamp res res 0 res res 0
ballast stage design AN2982 16/31 doc id 15599 rev 1 the run and preheating frequencies are calculated using the values calculated in equation 33: equation 33 figure 11. resonance curves the maximum striking current is equal to: equation 34 this current is also the saturation current of the ballast choke (i sat,ballast > 2.2 a). limiting the current to this value, the lamp voltage is limited to 700 vac (v cres,max > 700 vac). the half-bridge current sense resistor is chosen according to: equation 35 khz 5 . 72 v 2 v 2 1 f f khz 100 f khz 86 v v 2 1 f f khz 5 . 48 2 i 2 q z v 4 4 q 1 2 q 1 2 f f ign out 0 ign pre pre out 0 pre 2 run 0 out 2 2 2 0 run ? ? + = = > + = = ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? = !-v apk 121 . 2 f f f f 1 q f f q 1 z v 2 i 2 0 ign 2 2 0 ign 2 0 ign 0 out ign , ballast = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? = = = = 7543 . 0 a 121 . 2 v 6 . 1 i v r ign , ballast hbcsh hbcs r pfccs 0.33 =
AN2982 ballast stage design doc id 15599 rev 1 17/31 the rms value of one side of the half bridge is equal to: equation 36 the power dissipation of the half-bridge current sense resistor is equal to: equation 37 a blocking capacitor c block = 100 nf (400 vac) is used. the choke form factor is an ef25 core (a e = 52 mm 2 , l e = 58 mm, material n87 or equivalent having b max <300 mt). its design parameters are as follows: equation 38 for this component a multi-conductor wire is also used to reduce the hf equivalent resistance, and therefore the power dissipation. 2.2 selection of parameters figure 12. parameters setting block c osc = 1 nf (5% or better) is chosen. the following constant values are calculated (c osc in pf): a 3465 . 0 f f f f 1 q f f q 1 z v 2 2 1 2 i i 2 0 run 2 2 0 run 2 0 run 0 out pk , ballast rms , hb = ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? = mw 100 i r p 2 hbcs hbcs rms , hbcs < ? mm 37 . 3 l a n 2 l turns / nh 8 . 38 n l a turns 183 a b l i n e 2 0 gap 2 2 l e max max = = ? ? ? ? ? ? ? = = = = !-v
ballast stage design AN2982 18/31 doc id 15599 rev 1 equation 39 equation 40 given the run frequency and the preheatin g frequency (both in khz), the following components are found: equation 41 an ignition time equal to 50 ms is obtained using a c ign corresponding to: equation 42 a protection time equal to 120 ms is adopted, then: equation 43 the preheating time is equal to almost 1 s, therefore: equation 44 the closest commercial resistor for r d is 1.5 m . with this value t pre is equal to 865 ms. 2.3 half-bridge design the maximum power loss acceptable for half-bridge mosfets is equal to 500 mw. each mosfet experiences a conduction loss equal to: equation 45 with i rms 2 = 0.120 a 2 , a maximum r ds(on) = 2.08 is obtained. () 55 . 1209 c 10 6 . 499 k 872 . 0 osc 3 = ? = () 976 . 0 c 33 . 1 1 e 581 . 0 osc = ? = = ? ? = = ? ? ? ? ? ? ? ? = = = ? ? ? ? ? ? ? ? = k 9 . 24 k 86 . 12 r k 86 . 12 r r k 86 . 12 f k r // r k 7 . 26 r k 99 . 26 f k r run run pre e 1 pre run pre run e 1 run run = ign pre ign c r 3 t c ign 680nf = c d 470nf = ? = d prot c 269740 t r d 1.755m = ? ? ? ? ? ? + = 5 . 1 63 . 4 ln c r i c 63 . 4 t d d tch d pre ( ) 2 rms ) on ( ds cond i r p ? = <0.25 w
AN2982 ballast stage design doc id 15599 rev 1 19/31 the following st mosfets meet these constraints: ?std5nk50z ?std6nk50z ? std7nm50n the std7nm50n has r ds(on) = 1.12 (at 100c), therefore the power dissipation related to the half-bridge mosfets is equal to almost 270 mw. the size of the boostrap capacitor can be ca lculated by solving the following equation: equation 46 where: v = v cc,min - v gate,min = 9.6 v - 8 v = 1.6 v v cc = 15 v - v f , v f = forward voltage of charge pump diode = 0.8 v q g = total gate charge of std7nm50n = 12 nc c gate = q g /v cc = 845 pf c boot,min = 6.6 nf is obtained a c boot = 100 nf is selected and the voltage drop is equal to v = 120 mv. the charging time of the capacitor is calculated to check if v is compensated during the on-time of the low side. the time the capacitor takes to charge to 95% of v cc starting from 0 is equal to: equation 47 the time the capacitor takes to charge to 95% of v cc minus 120 mv starting from 0 is equal to: equation 48 the difference t 0 - t 1 = 4 s is smaller than the minimum on-time equal to: equation 49 the selected capacitor is able to co rrectly supply the high-side driver. v v v c c c cc cc min , boot min , boot gate ? ? = + s 75 nf 100 250 3 c r 3 t boot boot 0 = ? ? = ? ? = s 71 c r 839 . 2 v 12 . 0 v 95 . 0 1 ln c r t boot boot cc cc boot boot 1 = ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? = s 11 . 4 t f 2 1 t max , dead pre min , on = ? =
ballast stage design AN2982 20/31 doc id 15599 rev 1 2.4 end of life detection in this design the blocking capacito r to ground configuration is chosen. figure 13. blocking capacitor to ground topology the tracking configuration with a window of amplitude equal to 240 mv is selected, connecting eolp to ground with r eolp = 240 k . the eol pin detects the blocking capacitor voltage by means of a voltage divider that, in normal conditions, sets its voltage to the same value as the ctr pin: equation 50 choosing the total upper re sistor value equal to r eol1 = 1.36 m (2x680 k ), and with the steady-state value of the blocking capacitor voltage equal to v out /2, the lower resistor is calculated as: equation 51 a c eol = 10 nf capacitor is used to filter the lamp frequency, maintaining the ripple. the obtained cutoff frequency is calculated higher than 100 hz, but lower than 49 khz. equation 52 !-v eol ctrh ctrl ctrl out 0 , ctr v v 03 . 3 r r r v v = + = = ? = k 9 . 19 v 2 v v 2 r r eol out eol 1 eol 2 eol r eol2 20 k = hz 796 c r 2 1 f eol 2 eol eol , c = ? ?
AN2982 ballast stage design doc id 15599 rev 1 21/31 2.5 ic power supply design the ic current consumption depends on both the pfc frequency and half-bridge frequency. in the worst case, the mean value of the pfc frequency is equal to 162 khz and the maximum half-bridge frequency is equal to 90 khz. with these values the maximum supply current is approximately equal to: equation 53 this current is delivered to the ic by means of a charge pump connected to the middle point of the half bridge. figure 14. charge pump network and startup the current delivered by the charge pump capacitor is approximately: equation 54 where: equation 55 and rearranging the terms: equation 56 the startup network works also as a detector of lamp presence. this feature can be implemented by placing one or both of the la mp cathodes along the startup network path. if the lamp is absent, the ic cannot start. ma 11 56 . 4 f 0373 . 0 f 0192 . 0 i khz ma pre khz pfc cc + + ? = !-v cc run rise pk , cp cp i f t i i ? ? = rise out cp pk , cp t v c i = = ? pf 558 f v i c run out cp cp c cp 1nf =
ballast stage design AN2982 22/31 doc id 15599 rev 1 the minimum startup current of the l6585de is equal to i cc,on = 370 a. this current has to be delivered to the ic at the minimum input voltage (125 vpk), therefore a total resistance equal to: equation 57 the network is divided into 5 x 68 k resistors in order to avoid damage due to the lamp striking voltage. a c1 = 10 f followed by a 100 nf ceramic capacitor is used as the v cc bulk capacitor. = = k 337 i v r on , cc min , in tot , su
AN2982 demonstration board schematic and bill of material doc id 15599 rev 1 23/31 3 demonstration board schematic and bill of material figure 15. steval-ilb005v2 schematic !-v
demonstration board schematic and bill of material AN2982 24/31 doc id 15599 rev 1 table 2. bom reference value note r1 681 k r mult,hi r2 681 k r3 681 k r4 16.2 k r mult,lo r5 2.2 m r inv,hi r6 2.2 m r7 2.2 m r8 39.2 k r inv,lo r9 n.m. r10 75 k r zcd r11 47 pfc mosfet gate resistor r12 220 pfc current sense filtering resistor r13 825 k r ctr,hi r14 825 k r15 825 k r16 18 k r ctr,lo r18 26.1 k r run r19 29.4 k r pre r20 1.5 m r d r21 0r0 r22 240 k r eolp r23 0r0 r24 47 high-side mosfet gate resistor r25 47 low-side mosfet gate resistor r26 3.3 charge pump limiting resistor r27 3.3 r28 68 k startup network r29 68 k r30 560 k r eol,hi (1) r31 120 k r32 20.5 k r eol,lo r33 68 k startup network r34 68 k r35 68 k
AN2982 demonstration board schematic and bill of material doc id 15599 rev 1 25/31 r40 680 k r eol,hi (2) r41 n.m. rs1 0.33 ? 0.5 w r pfccs rs2 0.82 ? 0.5 w r hbcs c1 22 f ? 450 v c out ca1 0r0 c2 470 nf ? 305 vac c in c3 4.7 nf mult filtering capacitor c4 1 nf pfccs filtering capacitor c5 1 f c comp c6 n.m. c7 10 nf ctr filtering capacitor c8 1 nf - 1% c osc c9 1 f c ign c10 470 nf c d c11 100 nf c boot c12 1 nf - 630vdc c cp c13 10 f c vcc c14 100 nf c vcc,b c15 4.7 nf - 2 kv c res c16 100 nf - 630vdc c block c17 10 nf eol filtering capacitor c18 1 nf c20 100 nf, x2, 275vac differential mode emi filter c21 100 nf, x2, 275vac differential mode emi filter c22 1 nf y1 common mode emi filter (capacitive) c23 1 nf y1 common mode emi filter (capacitive) c24 0r0 d1 stth1l06 boost diode d2 1n4148 charge pump forward diode d3 1n4148 pfc gate speed-up diode dz1 bzx84c15 charge pump free-wheeling zener diode dz2 0r0 dz3 0r0 dz4 n.m. table 2. bom (continued) reference value note
demonstration board schematic and bill of material AN2982 26/31 doc id 15599 rev 1 3.1 demonstration board performances b1 2kbp06m rect ifier bridge u1 l6585de ballast controller q1 std7nm50n pfc mosfet q2 std7nm50n half-bridge high-side mosfet q3 std7nm50n half-bridge low-side mosfet t1 1.5 mh - 2.6 a pfc transformer ? epcos b78313p8140 t2 2 x 68 mh - 0.9 a common mode emi filter ? epcos b82733f2901 l1 1.3 mh - 2.6 a ballast choke ? itacoil e2543-h f1 t 2 a ? 250 vac fuse rt1 ntc 5 inrush current limiter table 2. bom (continued) reference value note figure 16. input performance - power factor figure 17. input performance - total harmonic distortion !-v 34%6!, ),"6 0& 6in6ac 0& !-v 34%6!, ),"6 4($ 6in6ac 4($ figure 18. emi spectrum at 277 vac figure 19. emi spectrum at 88 vac !-v !-v
AN2982 demonstration board schematic and bill of material doc id 15599 rev 1 27/31 3.2 ballast stage performance and reliability figure 20 shows the lamp parameters. small discrepancies between theoretical and real measurements are due to the tolerance of the passive components of the resonance network (l res and c res ). figure 20. steady-state lamp parameters figure 21 summarizes the t ch sequences during preheating and protections. during the open lamp test, t ch voltage (lower trace) sets the preheating time (t pre = 805 ms). after that the lamp voltage (upper trac e) increases up to the maximum value allowed by the hbcs resistor (740 vrms). the subsequent protection time is shorter than the preheating time (120 ms). figure 21. startup sequence with open lamp protection in figure 22 a close-up of the waveforms during a ballast choke saturation is shown. the upper graph illustrates the lamp parameters. while the lamp voltage remains essentially sinusoidal, the lamp current be comes triangular cycle by cycl e. the lower trace illustrates the half-bridge current sense voltage (v hbcs ). as soon as this voltage reaches 2.75 v, the application is immediately stopped. the saturation effect does not have a definite threshold. once the current is close to saturation, the inductance value starts to decre ase slowly and constantly, therefore a current !-v !-v
demonstration board schematic and bill of material AN2982 28/31 doc id 15599 rev 1 limiting that maintains the frequency constant is not suitable to counter this effect. actually the application should be stopped as soon as the saturation effect is detected. figure 22. ballast anti-choke saturation protection asymmetrical ageing of the lamp is detected by the eol pin. figure 23 and 24 illustrate the behavior of this protection. in the upper trace the lamp voltage and t ch voltage are shown. when the lamp starts ageing, the lamp voltage increases in one direction. the eol voltage (lower trace) moves t ogether with the blocking capacitor voltage. once the difference between the ctr voltage and the eol voltage is higher than 240 mv, a t ch cycle is started and the application is stopped if this situation persists. figure 23. eol protection (positive deviation) !-v !-v
AN2982 demonstration board schematic and bill of material doc id 15599 rev 1 29/31 figure 24. eol protection (negative deviation) !-v
revision history AN2982 30/31 doc id 15599 rev 1 4 revision history table 3. document revision history date revision changes 15-mar-2010 1 initial release.
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